UNIX CPU Diagnostics

CPU Usage

Linux

top

Once in top.. hit 'z' to colourize, '1' to show individual cpu cores, '?' for other options

htop

htop

Processes using most CPU

dstat -c --top-cpu

AIX

topas

tprof -skeu -x sleep 10

tprof -skex sleep 10

CPU Load

Load average generally display three figures representing the average load over the last 1 minute, 5 minutes, and 15 minutes. The load average is displayed by various tools (w,top, htop), but this is probably the simplest...

uptime

On Linux,  system load includes threads in Runnable (R) and in Uninterruptible sleep (D) states (typically disk I/O). On other flavours of UNIX this is usually just R (not D).

Load should be less than the number of cores in your system. i.e. On a single core machine you would want load to be less than 1. On a quad core machine you would want load to be less than 4. 

We can see which users are contributing to system load using...

ps -eo s,user | grep ^[RD] | sort | uniq -c | sort -nbr | head -20

On Linux,  system load includes threads in Runnable (R) and in Uninterruptible sleep (D) states (typically disk I/O). On other flavours of UNIX this is usually just R (not D).

To see what they are running use...

ps -eo s,user,cmd | grep ^[RD] | sort | uniq -c | sort -nbr | head -20

On Linux,  system load includes threads in Runnable (R) and in Uninterruptible sleep (D) states (typically disk I/O). On other flavours of UNIX this is usually just R (not D).

The vmstat command also gives some useful information. The first two columns under "procs" on Linux or "kthr" on AIX show runnable (r) and blocked (b) processes/threads. The value of "r" should generally be less than or equal to the number of logical CPUs. The value of "b" should generally be zero.

vmstat -wWI 2 10

CPU Benchmarking

Sysbench

sysbench --test=cpu run

sudo apt install sysbench

CPU Blowfish

Screenshot is from hardinfo. This tends to be available in Ubuntu as "System Profiler and Benchmark"

Geekbench

TODO

CPU Information

nproc and getconf are part of coreutils, dmidecode, hwinfo and inxi are standalone

CPU Count

The output from nproc and getconf below shows the total number of CPU threads. As you can see from the lscpu example later on this page, in this case the output of 12 is the result of having 1 socket with 6 cores each with 2 threads.

nproc --all

getconf _NPROCESSORS_ONLN 

12
12

CPU Information

lscpu

See Flags/Capabilities section later on this page for description of flags.
Architecture:            x86_64  CPU op-mode(s):        32-bit, 64-bit  Address sizes:         46 bits physical, 48 bits virtual  Byte Order:            Little EndianCPU(s):                  12  On-line CPU(s) list:   0-11Vendor ID:               GenuineIntel  Model name:            Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz    CPU family:          6    Model:               45    Thread(s) per core:  2    Core(s) per socket:  6    Socket(s):           1    Stepping:            7    CPU max MHz:         3500.0000    CPU min MHz:         1200.0000    BogoMIPS:            5785.91    Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht                          tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpui                         d aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2a                         pic popcnt tsc_deadline_timer aes xsave avx lahf_lm epb pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ep                         t vpid xsaveopt dtherm ida arat pln pts md_clear flush_l1dVirtualisation features:   Virtualisation:        VT-xCaches (sum of all):       L1d:                   192 KiB (6 instances)  L1i:                   192 KiB (6 instances)  L2:                    1.5 MiB (6 instances)  L3:                    15 MiB (1 instance)NUMA:                      NUMA node(s):          1  NUMA node0 CPU(s):     0-11Vulnerabilities:           Itlb multihit:         KVM: Mitigation: VMX disabled  L1tf:                  Mitigation; PTE Inversion; VMX conditional cache flushes, SMT vulnerable  Mds:                   Mitigation; Clear CPU buffers; SMT vulnerable  Meltdown:              Mitigation; PTI  Mmio stale data:       Unknown: No mitigations  Retbleed:              Not affected  Spec store bypass:     Mitigation; Speculative Store Bypass disabled via prctl and seccomp  Spectre v1:            Mitigation; usercopy/swapgs barriers and __user pointer sanitization  Spectre v2:            Mitigation; Retpolines, IBPB conditional, IBRS_FW, STIBP conditional, RSB filling, PBRSB-eIBRS Not affected  Srbds:                 Not affected  Tsx async abort:       Not affected

cat /proc/cpuinfo

Similar information to that shown below is repeated for each thread.
processor : 0vendor_id : GenuineIntelcpu family : 6model : 45model name : Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHzstepping : 7microcode : 0x71acpu MHz : 1200.000cache size : 15360 KBphysical id : 0siblings : 12core id : 0cpu cores : 6apicid : 0initial apicid : 0fpu : yesfpu_exception : yescpuid level : 13wp : yesflags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx lahf_lm epb pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid xsaveopt dtherm ida arat pln pts md_clear flush_l1dvmx flags : vnmi preemption_timer invvpid ept_x_only ept_1gb flexpriority tsc_offset vtpr mtf vapic ept vpid unrestricted_guest plebugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs itlb_multihit mmio_unknownbogomips : 5785.91clflush size : 64cache_alignment : 64address sizes : 46 bits physical, 48 bits virtualpower management:

sudo dmidecode -t 4

# dmidecode 3.3Getting SMBIOS data from sysfs.SMBIOS 2.7 present.
Handle 0x0004, DMI type 4, 42 bytesProcessor Information Socket Designation: CPU0 Type: Central Processor Family: Xeon Manufacturer: Intel ID: D7 06 02 00 FF FB EB BF Signature: Type 0, Family 6, Model 45, Stepping 7 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) DS (Debug store) ACPI (ACPI supported) MMX (MMX technology supported) FXSR (FXSAVE and FXSTOR instructions supported) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) SS (Self-snoop) HTT (Multi-threading) TM (Thermal monitor supported) PBE (Pending break enabled) Version: Intel(R) Xeon(R) CPU E5-2667 @ 2.90GHz Voltage: 1.1 V External Clock: 100 MHz Max Speed: 3800 MHz Current Speed: 2900 MHz Status: Populated, Enabled Upgrade: Socket LGA2011 L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Core Count: 6 Core Enabled: 6 Thread Count: 12 Characteristics: 64-bit capable Multi-Core Hardware Thread Execute Protection Enhanced Virtualization Power/Performance Control
Handle 0x0008, DMI type 4, 42 bytesProcessor Information Socket Designation: CPU1 Type: Central Processor Family: Xeon Manufacturer: Intel ID: 00 00 00 00 00 00 00 00 Signature: Type 0, Family 0, Model 0, Stepping 0 Flags: None Version: Intel(R) Xeon(R) CPU E5-2667 @ 2.90GHz Voltage: 0.2 V External Clock: 100 MHz Max Speed: 4000 MHz Current Speed: Unknown Status: Unpopulated Upgrade: Socket LGA2011 L1 Cache Handle: Not Provided L2 Cache Handle: Not Provided L3 Cache Handle: Not Provided Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Core Count: 101 Core Enabled: 85 Thread Count: 63 Characteristics: Multi-Core Enhanced Virtualization Power/Performance Control
It's not very clear what the stanza for CPU1 is actually telling us, but the lshw output (see below) would suggest it's an empty socket.

sudo lshw -class processor

See Flags/Capabilities section later on this page for description of flags.
  *-cpu:0                          description: CPU       product: Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz       vendor: Intel Corp.       physical id: 4       bus info: cpu@0       version: 6.45.7       slot: CPU0       size: 2764MHz       capacity: 3800MHz       width: 64 bits       clock: 100MHz       capabilities: lm fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx lahf_lm epb pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid xsaveopt dtherm ida arat pln pts md_clear flush_l1d cpufreq       configuration: cores=6 enabledcores=6 microcode=1818 threads=12  *-cpu:1 DISABLED       description: CPU [empty]       product: Xeon       vendor: Intel       physical id: 1       version: Intel(R) Xeon(R) CPU E5-2667 @ 2.90GHz       slot: CPU1       configuration: cores=101 enabledcores=85 threads=63

sudo dmidecode -t 4 | egrep -i 'core (count|enabled)|thread count|Version'

Version: Intel(R) Xeon(R) CPU E5-2667 @ 2.90GHz Core Count: 6 Core Enabled: 6 Thread Count: 12 Version: Intel(R) Xeon(R) CPU E5-2667 @ 2.90GHz Core Count: 101 Core Enabled: 85 Thread Count: 63

hwinfo --cpu --short 

cpu:                                                                                   Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 3100 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1825 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz                       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz, 1200 MHz

hwinfo --cpu

Similar information to that shown below is repeated for each thread.
01: None 00.0: 10103 CPU                                          [Created at cpu.465]  Unique ID: rdCR.j8NaKXDZtZ6  Hardware Class: cpu  Arch: X86-64  Vendor: "GenuineIntel"  Model: 6.45.7 "Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz"  Features: fpu,vme,de,pse,tsc,msr,pae,mce,cx8,apic,sep,mtrr,pge,mca,cmov,pat,pse36,clflush,dts,acpi,mmx,fxsr,sse,sse2,ss,ht,tm,pbe,syscall,nx,pdpe1gb,rdtscp,lm,constant_tsc,arch_perfmon,pebs,bts,rep_good,nopl,xtopology,nonstop_tsc,cpuid,aperfmperf,pni,pclmulqdq,dtes64,monitor,ds_cpl,vmx,smx,est,tm2,ssse3,cx16,xtpr,pdcm,pcid,dca,sse4_1,sse4_2,x2apic,popcnt,tsc_deadline_timer,aes,xsave,avx,lahf_lm,epb,pti,ssbd,ibrs,ibpb,stibp,tpr_shadow,vnmi,flexpriority,ept,vpid,xsaveopt,dtherm,ida,arat,pln,pts,md_clear,flush_l1d  Clock: 1200 MHz  BogoMips: 5785.91  Cache: 15360 kb  Units/Processor: 32  Config Status: cfg=new, avail=yes, need=no, active=unknown

inxi -Cx -c 5

CPU:  Info: 6-core model: Intel Xeon E5-2667 0 bits: 64 type: MT MCP    arch: Sandy Bridge rev: 7 cache: L1: 384 KiB L2: 1.5 MiB L3: 15 MiB  Speed (MHz): avg: 1602 high: 2314 min/max: 1200/3500 cores: 1: 1410    2: 1533 3: 1453 4: 2314 5: 1668 6: 1522 7: 1432 8: 1820 9: 1522 10: 1636    11: 1364 12: 1556 bogomips: 69430  Flags: avx ht lm nx pae sse sse2 sse3 sse4_1 sse4_2 ssse3 vmx

cpuid -1

The -1 flag stops cpuid returning duplicate information (if you know all CPUs are the same)
sudo apt install cpuid
CPU:   vendor_id = "GenuineIntel"   version information (1/eax):      processor type  = primary processor (0)      family          = 0x6 (6)      model           = 0xd (13)      stepping id     = 0x7 (7)      extended family = 0x0 (0)      extended model  = 0x2 (2)      (family synth)  = 0x6 (6)      (model synth)   = 0x2d (45)      (simple synth)  = Intel Core (unknown type) (Sandy Bridge-E C2/M1) {Sandy Bridge}, 32nm   miscellaneous (1/ebx):      process local APIC physical ID = 0x7 (7)      maximum IDs for CPUs in pkg    = 0x20 (32)      CLFLUSH line size              = 0x8 (8)      brand index                    = 0x0 (0)   brand id = 0x00 (0): unknown   feature information (1/edx):      x87 FPU on chip                        = true      VME: virtual-8086 mode enhancement     = true      DE: debugging extensions               = true      PSE: page size extensions              = true      TSC: time stamp counter                = true      RDMSR and WRMSR support                = true      PAE: physical address extensions       = true      MCE: machine check exception           = true      CMPXCHG8B inst.                        = true      APIC on chip                           = true      SYSENTER and SYSEXIT                   = true      MTRR: memory type range registers      = true      PTE global bit                         = true      MCA: machine check architecture        = true      CMOV: conditional move/compare instr   = true      PAT: page attribute table              = true      PSE-36: page size extension            = true      PSN: processor serial number           = false      CLFLUSH instruction                    = true      DS: debug store                        = true      ACPI: thermal monitor and clock ctrl   = true      MMX Technology                         = true      FXSAVE/FXRSTOR                         = true      SSE extensions                         = true      SSE2 extensions                        = true      SS: self snoop                         = true      hyper-threading / multi-core supported = true      TM: therm. monitor                     = true      IA64                                   = false      PBE: pending break event               = true   feature information (1/ecx):      PNI/SSE3: Prescott New Instructions     = true      PCLMULDQ instruction                    = true      DTES64: 64-bit debug store              = true      MONITOR/MWAIT                           = true      CPL-qualified debug store               = true      VMX: virtual machine extensions         = true      SMX: safer mode extensions              = true      Enhanced Intel SpeedStep Technology     = true      TM2: thermal monitor 2                  = true      SSSE3 extensions                        = true      context ID: adaptive or shared L1 data  = false      SDBG: IA32_DEBUG_INTERFACE              = false      FMA instruction                         = false      CMPXCHG16B instruction                  = true      xTPR disable                            = true      PDCM: perfmon and debug                 = true      PCID: process context identifiers       = true      DCA: direct cache access                = true      SSE4.1 extensions                       = true      SSE4.2 extensions                       = true      x2APIC: extended xAPIC support          = true      MOVBE instruction                       = false      POPCNT instruction                      = true      time stamp counter deadline             = true      AES instruction                         = true      XSAVE/XSTOR states                      = true      OS-enabled XSAVE/XSTOR                  = true      AVX: advanced vector extensions         = true      F16C half-precision convert instruction = false      RDRAND instruction                      = false      hypervisor guest status                 = false   cache and TLB information (2):      0x5a: data TLB: 2M/4M pages, 4-way, 32 entries      0x03: data TLB: 4K pages, 4-way, 64 entries      0x76: instruction TLB: 2M/4M pages, fully, 8 entries      0xff: cache data is in CPUID leaf 4      0xb2: instruction TLB: 4K, 4-way, 64 entries      0xf0: 64 byte prefetching      0xca: L2 TLB: 4K pages, 4-way, 512 entries   processor serial number = 0002-06D7-0000-0000-0000-0000   deterministic cache parameters (4):      --- cache 0 ---      cache type                         = data cache (1)      cache level                        = 0x1 (1)      self-initializing cache level      = true      fully associative cache            = false      maximum IDs for CPUs sharing cache = 0x1 (1)      maximum IDs for cores in pkg       = 0xf (15)      system coherency line size         = 0x40 (64)      physical line partitions           = 0x1 (1)      ways of associativity              = 0x8 (8)      number of sets                     = 0x40 (64)      WBINVD/INVD acts on lower caches   = false      inclusive to lower caches          = false      complex cache indexing             = false      number of sets (s)                 = 64      (size synth)                       = 32768 (32 KB)      --- cache 1 ---      cache type                         = instruction cache (2)      cache level                        = 0x1 (1)      self-initializing cache level      = true      fully associative cache            = false      maximum IDs for CPUs sharing cache = 0x1 (1)      maximum IDs for cores in pkg       = 0xf (15)      system coherency line size         = 0x40 (64)      physical line partitions           = 0x1 (1)      ways of associativity              = 0x8 (8)      number of sets                     = 0x40 (64)      WBINVD/INVD acts on lower caches   = false      inclusive to lower caches          = false      complex cache indexing             = false      number of sets (s)                 = 64      (size synth)                       = 32768 (32 KB)      --- cache 2 ---      cache type                         = unified cache (3)      cache level                        = 0x2 (2)      self-initializing cache level      = true      fully associative cache            = false      maximum IDs for CPUs sharing cache = 0x1 (1)      maximum IDs for cores in pkg       = 0xf (15)      system coherency line size         = 0x40 (64)      physical line partitions           = 0x1 (1)      ways of associativity              = 0x8 (8)      number of sets                     = 0x200 (512)      WBINVD/INVD acts on lower caches   = false      inclusive to lower caches          = false      complex cache indexing             = false      number of sets (s)                 = 512      (size synth)                       = 262144 (256 KB)      --- cache 3 ---      cache type                         = unified cache (3)      cache level                        = 0x3 (3)      self-initializing cache level      = true      fully associative cache            = false      maximum IDs for CPUs sharing cache = 0x1f (31)      maximum IDs for cores in pkg       = 0xf (15)      system coherency line size         = 0x40 (64)      physical line partitions           = 0x1 (1)      ways of associativity              = 0x14 (20)      number of sets                     = 0x3000 (12288)      WBINVD/INVD acts on lower caches   = false      inclusive to lower caches          = true      complex cache indexing             = true      number of sets (s)                 = 12288      (size synth)                       = 15728640 (15 MB)      --- cache 4 ---      cache type                         = no more caches (0)   MONITOR/MWAIT (5):      smallest monitor-line size (bytes)       = 0x40 (64)      largest monitor-line size (bytes)        = 0x40 (64)      enum of Monitor-MWAIT exts supported     = true      supports intrs as break-event for MWAIT  = true      number of C0 sub C-states using MWAIT    = 0x0 (0)      number of C1 sub C-states using MWAIT    = 0x2 (2)      number of C2 sub C-states using MWAIT    = 0x1 (1)      number of C3 sub C-states using MWAIT    = 0x1 (1)      number of C4 sub C-states using MWAIT    = 0x2 (2)      number of C5 sub C-states using MWAIT    = 0x0 (0)      number of C6 sub C-states using MWAIT    = 0x0 (0)      number of C7 sub C-states using MWAIT    = 0x0 (0)   Thermal and Power Management Features (6):      digital thermometer                     = true      Intel Turbo Boost Technology            = true      ARAT always running APIC timer          = true      PLN power limit notification            = true      ECMD extended clock modulation duty     = true      PTM package thermal management          = true      HWP base registers                      = false      HWP notification                        = false      HWP activity window                     = false      HWP energy performance preference       = false      HWP package level request               = false      HDC base registers                      = false      Intel Turbo Boost Max Technology 3.0    = false      HWP capabilities                        = false      HWP PECI override                       = false      flexible HWP                            = false      IA32_HWP_REQUEST MSR fast access mode   = false      HW_FEEDBACK MSRs supported              = false      ignoring idle logical processor HWP req = false      enhanced hardware feedback interface    = false      digital thermometer thresholds          = 0x2 (2)      hardware coordination feedback          = true      ACNT2 available                         = false      performance-energy bias capability      = true      number of enh hardware feedback classes = 0x0 (0)      performance capability reporting        = false      energy efficiency capability reporting  = false      size of feedback struct (4KB pages)     = 0x1 (1)      index of CPU's row in feedback struct   = 0x0 (0)   extended feature flags (7):      FSGSBASE instructions                    = false      IA32_TSC_ADJUST MSR supported            = false      SGX: Software Guard Extensions supported = false      BMI1 instructions                        = false      HLE hardware lock elision                = false      AVX2: advanced vector extensions 2       = false      FDP_EXCPTN_ONLY                          = false      SMEP supervisor mode exec protection     = false      BMI2 instructions                        = false      enhanced REP MOVSB/STOSB                 = false      INVPCID instruction                      = false      RTM: restricted transactional memory     = false      RDT-CMT/PQoS cache monitoring            = false      deprecated FPU CS/DS                     = false      MPX: intel memory protection extensions  = false      RDT-CAT/PQE cache allocation             = false      AVX512F: AVX-512 foundation instructions = false      AVX512DQ: double & quadword instructions = false      RDSEED instruction                       = false      ADX instructions                         = false      SMAP: supervisor mode access prevention  = false      AVX512IFMA: fused multiply add           = false      PCOMMIT instruction                      = false      CLFLUSHOPT instruction                   = false      CLWB instruction                         = false      Intel processor trace                    = false      AVX512PF: prefetch instructions          = false      AVX512ER: exponent & reciprocal instrs   = false      AVX512CD: conflict detection instrs      = false      SHA instructions                         = false      AVX512BW: byte & word instructions       = false      AVX512VL: vector length                  = false      PREFETCHWT1                              = false      AVX512VBMI: vector byte manipulation     = false      UMIP: user-mode instruction prevention   = false      PKU protection keys for user-mode        = false      OSPKE CR4.PKE and RDPKRU/WRPKRU          = false      WAITPKG instructions                     = false      AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND  = false      CET_SS: CET shadow stack                 = false      GFNI: Galois Field New Instructions      = false      VAES instructions                        = false      VPCLMULQDQ instruction                   = false      AVX512_VNNI: neural network instructions = false      AVX512_BITALG: bit count/shiffle         = false      TME: Total Memory Encryption             = false      AVX512: VPOPCNTDQ instruction            = false      LA57: 57-bit addrs & 5-level paging      = false      BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)      RDPID: read processor D supported        = false      KL: key locker                           = false      bus lock detection                       = false      CLDEMOTE supports cache line demote      = false      MOVDIRI instruction                      = false      MOVDIR64B instruction                    = false      ENQCMD instruction                       = false      SGX_LC: SGX launch config supported      = false      PKS: supervisor protection keys          = false      AVX512_4VNNIW: neural network instrs     = false      AVX512_4FMAPS: multiply acc single prec  = false      fast short REP MOV                       = false      UINTR: user interrupts                   = false      AVX512_VP2INTERSECT: intersect mask regs = false      SRBDS mitigation MSR available           = false      VERW MD_CLEAR microcode support          = true      RTM transaction always aborts            = false      TSX_FORCE_ABORT                          = false      SERIALIZE instruction                    = false      hybrid part                              = false      TSXLDTRK: TSX suspend load addr tracking = false      PCONFIG instruction                      = false      LBR: architectural last branch records   = false      CET_IBT: CET indirect branch tracking    = false      AMX-BF16: tile bfloat16 support          = false      AVX512_FP16: fp16 support                = false      AMX-TILE: tile architecture support      = false      AMX-INT8: tile 8-bit integer support     = false      IBRS/IBPB: indirect branch restrictions  = true      STIBP: 1 thr indirect branch predictor   = true      L1D_FLUSH: IA32_FLUSH_CMD MSR            = true      IA32_ARCH_CAPABILITIES MSR               = false      IA32_CORE_CAPABILITIES MSR               = false      SSBD: speculative store bypass disable   = true   Direct Cache Access Parameters (9):      PLATFORM_DCA_CAP MSR bits = 1   Architecture Performance Monitoring Features (0xa):      version ID                               = 0x3 (3)      number of counters per logical processor = 0x4 (4)      bit width of counter                     = 0x30 (48)      length of EBX bit vector                 = 0x7 (7)      core cycle event                         = available      instruction retired event                = available      reference cycles event                   = available      last-level cache ref event               = available      last-level cache miss event              = available      branch inst retired event                = available      branch mispred retired event             = available      top-down slots event                     = not available      fixed counter  0 supported               = false      fixed counter  1 supported               = false      fixed counter  2 supported               = false      fixed counter  3 supported               = false      fixed counter  4 supported               = false      fixed counter  5 supported               = false      fixed counter  6 supported               = false      fixed counter  7 supported               = false      fixed counter  8 supported               = false      fixed counter  9 supported               = false      fixed counter 10 supported               = false      fixed counter 11 supported               = false      fixed counter 12 supported               = false      fixed counter 13 supported               = false      fixed counter 14 supported               = false      fixed counter 15 supported               = false      fixed counter 16 supported               = false      fixed counter 17 supported               = false      fixed counter 18 supported               = false      fixed counter 19 supported               = false      fixed counter 20 supported               = false      fixed counter 21 supported               = false      fixed counter 22 supported               = false      fixed counter 23 supported               = false      fixed counter 24 supported               = false      fixed counter 25 supported               = false      fixed counter 26 supported               = false      fixed counter 27 supported               = false      fixed counter 28 supported               = false      fixed counter 29 supported               = false      fixed counter 30 supported               = false      fixed counter 31 supported               = false      number of contiguous fixed counters      = 0x3 (3)      bit width of fixed counters              = 0x30 (48)      anythread deprecation                    = false   x2APIC features / processor topology (0xb):      extended APIC ID                      = 7      --- level 0 ---      level number                          = 0x0 (0)      level type                            = thread (1)      bit width of level                    = 0x1 (1)      number of logical processors at level = 0x2 (2)      --- level 1 ---      level number                          = 0x1 (1)      level type                            = core (2)      bit width of level                    = 0x5 (5)      number of logical processors at level = 0xc (12)      --- level 2 ---      level number                          = 0x2 (2)      level type                            = invalid (0)      bit width of level                    = 0x0 (0)      number of logical processors at level = 0x0 (0)   XSAVE features (0xd/0):      XCR0 valid bit field mask               = 0x0000000000000007         XCR0 supported: x87 state            = true         XCR0 supported: SSE state            = true         XCR0 supported: AVX state            = true         XCR0 supported: MPX BNDREGS          = false         XCR0 supported: MPX BNDCSR           = false         XCR0 supported: AVX-512 opmask       = false         XCR0 supported: AVX-512 ZMM_Hi256    = false         XCR0 supported: AVX-512 Hi16_ZMM     = false         IA32_XSS supported: PT state         = false         XCR0 supported: PKRU state           = false         XCR0 supported: CET_U state          = false         XCR0 supported: CET_S state          = false         IA32_XSS supported: HDC state        = false         IA32_XSS supported: UINTR state      = false         LBR supported                        = false         IA32_XSS supported: HWP state        = false         XTILECFG supported                   = false         XTILEDATA supported                  = false      bytes required by fields in XCR0        = 0x00000340 (832)      bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)   XSAVE features (0xd/1):      XSAVEOPT instruction                        = true      XSAVEC instruction                          = false      XGETBV instruction                          = false      XSAVES/XRSTORS instructions                 = false      XFD: extended feature disable supported     = false      SAVE area size in bytes                     = 0x00000000 (0)      IA32_XSS lower 32 bits valid bit field mask = 0x00000000      IA32_XSS upper 32 bits valid bit field mask = 0x00000000   AVX/YMM features (0xd/2):      AVX/YMM save state byte size             = 0x00000100 (256)      AVX/YMM save state byte offset           = 0x00000240 (576)      supported in IA32_XSS or XCR0            = XCR0 (user state)      64-byte alignment in compacted XSAVE     = false      XFD faulting supported                   = false   extended feature flags (0x80000001/edx):      SYSCALL and SYSRET instructions        = true      execution disable                      = true      1-GB large page support                = true      RDTSCP                                 = true      64-bit extensions technology available = true   Intel feature flags (0x80000001/ecx):      LAHF/SAHF supported in 64-bit mode     = true      LZCNT advanced bit manipulation        = false      3DNow! PREFETCH/PREFETCHW instructions = false   brand = "       Intel(R) Xeon(R) CPU E5-2667 0 @ 2.90GHz"   L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):      instruction # entries     = 0x0 (0)      instruction associativity = 0x0 (0)      data # entries            = 0x0 (0)      data associativity        = 0x0 (0)   L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):      instruction # entries     = 0x0 (0)      instruction associativity = 0x0 (0)      data # entries            = 0x0 (0)      data associativity        = 0x0 (0)   L1 data cache information (0x80000005/ecx):      line size (bytes) = 0x0 (0)      lines per tag     = 0x0 (0)      associativity     = 0x0 (0)      size (KB)         = 0x0 (0)   L1 instruction cache information (0x80000005/edx):      line size (bytes) = 0x0 (0)      lines per tag     = 0x0 (0)      associativity     = 0x0 (0)      size (KB)         = 0x0 (0)   L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):      instruction # entries     = 0x0 (0)      instruction associativity = L2 off (0)      data # entries            = 0x0 (0)      data associativity        = L2 off (0)   L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):      instruction # entries     = 0x0 (0)      instruction associativity = L2 off (0)      data # entries            = 0x0 (0)      data associativity        = L2 off (0)   L2 unified cache information (0x80000006/ecx):      line size (bytes) = 0x40 (64)      lines per tag     = 0x0 (0)      associativity     = 8-way (6)      size (KB)         = 0x100 (256)   L3 cache information (0x80000006/edx):      line size (bytes)     = 0x0 (0)      lines per tag         = 0x0 (0)      associativity         = L2 off (0)      size (in 512KB units) = 0x0 (0)   RAS Capability (0x80000007/ebx):      MCA overflow recovery support = false      SUCCOR support                = false      HWA: hardware assert support  = false      scalable MCA support          = false   Advanced Power Management Features (0x80000007/ecx):      CmpUnitPwrSampleTimeRatio = 0x0 (0)   Advanced Power Management Features (0x80000007/edx):      TS: temperature sensing diode           = false      FID: frequency ID control               = false      VID: voltage ID control                 = false      TTP: thermal trip                       = false      TM: thermal monitor                     = false      STC: software thermal control           = false      100 MHz multiplier control              = false      hardware P-State control                = false      TscInvariant                            = true      CPB: core performance boost             = false      read-only effective frequency interface = false      processor feedback interface            = false      APM power reporting                     = false      connected standby                       = false      RAPL: running average power limit       = false   Physical Address and Linear Address Size (0x80000008/eax):      maximum physical address bits         = 0x2e (46)      maximum linear (virtual) address bits = 0x30 (48)      maximum guest physical address bits   = 0x0 (0)   Extended Feature Extensions ID (0x80000008/ebx):      CLZERO instruction                       = false      instructions retired count support       = false      always save/restore error pointers       = false      INVLPGB instruction                      = false      RDPRU instruction                        = false      memory bandwidth enforcement             = false      MCOMMIT instruction                      = false      WBNOINVD instruction                     = false      IBPB: indirect branch prediction barrier = false      interruptible WBINVD, WBNOINVD           = false      IBRS: indirect branch restr speculation  = false      STIBP: 1 thr indirect branch predictor   = false      CPU prefers: IBRS always on              = false      CPU prefers: STIBP always on             = false      IBRS preferred over software solution    = false      IBRS provides same mode protection       = false      EFER[LMSLE] not supported                = false      INVLPGB supports TLB flush guest nested  = false      ppin processor id number supported       = false      SSBD: speculative store bypass disable   = false      virtualized SSBD                         = false      SSBD fixed in hardware                   = false      CPPC: collaborative processor perf ctrl  = false      PSFD: predictive store forward disable   = false      branch sampling feature support          = false   Size Identifiers (0x80000008/ecx):      number of CPU cores                 = 0x1 (1)      ApicIdCoreIdSize                    = 0x0 (0)      performance time-stamp counter size = 40 bits (0)   Feature Extended Size (0x80000008/edx):      max page count for INVLPGB instruction = 0x0 (0)      RDPRU instruction max input support    = 0x0 (0)   (multi-processing synth) = multi-core (c=6), hyper-threaded (t=2)   (multi-processing method) = Intel leaf 0xb   (APIC widths synth): CORE_width=5 SMT_width=1   (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1   (uarch synth) = Intel Sandy Bridge {Sandy Bridge}, 32nm   (synth) = Intel Xeon E5-1600/2600/4600 (Sandy Bridge-E C2/M1) {Sandy Bridge}, 32nm
Flags

















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CPU Information (AIX)

CPU SMT Type...

lparstat -i | grep ^Type

LPAR CPU usage Mode...

lparstat -i | grep ^Mode

LPAR CPU Entitlement...

lparstat -i | grep Entitled | grep -v of

Online Virtual CPUs...

lparstat -i | grep "Online Virtual"

Shared Pool ID...

lparstat -i | grep "Shared Pool ID"

Active CPUs in Pool...

lparstat -i | grep "Active CPUs in Pool"

CPU Type/Speed...

prtconf | grep "Processor Type"

prtconf -s

prtconf -c

Architecture  (32-bit or 64-bit)

arch

x86_64

uname -m

x86_64

getconf LONG_BIT

64

lscpu | grep Architecture

Architecture:                    x86_64

hwinfo --cpu | grep Arch | uniq

  Arch: X86-64
64-bit is also known as 'long mode' or 'lm', which opens up a few more options...grep flags /proc/cpuinfo | sort -ugrep -o -w 'lm' /proc/cpuinfo | sort -uSee Flags/Capabilities section later on this page

inxi -Cx | grep bits 

  Info: 6-core model: Intel Xeon E5-2667 0 bits: 64 type: MT MCP

Flags/Capabilities

FlagsThe Flags section of lscpu and several of the other commands show the capabilities of the cpu. In the examples above we have...
UNIX-CPU-Flags

SMT - Symmetric Multi-Threading

AIX

You can see details of SMT using the smtctl command (but this is only executable by 'root' and can be a bad thing if run with the wrong arguments... i.e. it can turn off SMT).

smtctl

This system is SMT capable.

This system supports up to 4 SMT threads per processor.

SMT is currently enabled.

SMT boot mode is not set.

SMT threads are bound to the same virtual processor.


proc0 has 4 SMT threads.

Bind processor 0 is bound with proc0

Bind processor 1 is bound with proc0

Bind processor 2 is bound with proc0

Bind processor 3 is bound with proc0

Things like OEM and topas see each thread as a cpu and therefore show 4 cpus, when in fact they are all just simultaneous threads on the same core... which can be very misleading... to make matters worse 4 threads cannot do the same work as 4 dedicated cores... so even cpu utilisation figures can be skewed... i.e. if you are running 1 transaction in 1 second on 1 thread, you won't be able to run 2 transactions in 1 second using 2 threads (but you might get 2 transactions in 1.5 seconds using 2 threads instead of the 2 transactions in 2 seconds that you would expect from a single thread... i.e. it makes better use of the cores than single threading but there are still bottlenecks that stop 2 transactions running at full speed through the same cpu core at the same time)... if you looked at topas whilst your hypothetical 1 transaction in 1 second was running on 1 thread you would see cpu utilisation of 25% on a core with 4 threads (which just isn't true).

Bibliography